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UM E-Theses Collection (澳門大學電子學位論文庫)
Category
Jiang, Yang
Title arrow_drop_up | Author | Supervisor | Issue Date | Degree |
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Clock-jitter insensitive circuit techniques in continuous-time sigma-delta modulators check Full Text |
Jiang, Yang | Sin, Sai-Weng | 2012. | Master |
Design of fully integrated fine-grained switched-capacitor DC-DC topologies in bulk CMOS check Full Text |
Jiang, Yang | Martins, Rui Paulo | 2018. | Doctoral |