UM E-Theses Collection (澳門大學電子學位論文庫)
Analysis and design of power-efficient voltage-controlled oscillators for wireless applications in nanoscale CMOS
English Abstract
The fast growing demand for higher data transfer rates and longer battery life requires the wireless devices to work at higher frequency for large bandwidth with low power consumption. The voltage-controlled oscillator (VCO), as one of the most critical building blocks in modern RF transceivers, is responsible to provide the local oscillator (LO) signals with high spectrum purity for data transmission and reception. As the frequency increases, it becomes more and more challenging to design a low phase-noise VCO with small power consumption while covering enough frequency tuning range, as a small inductor intrinsically results in lower LC-tank’s impedance that in return demands a larger bias current to secure an adequate output swing. Moreover, the VCO may also need to generate poly-phase LO signals with sufficient phase and amplitude accuracy for the modern RF transceiver to reject the received interference at image frequency and reduce the reciprocal mixing with LO harmonics. This thesis mainly focuses on low power, low phase-noise VCO design for wireless applications. Firstly, a differential VCO-buffer with enhanced load drivability is introduced for IEEE 802.11a/g WLAN applications. By stacking a PMOS-based source follower atop a NMOS-based LC-tank VCO, the current is reused by both the VCO core and buffer, which reduces the total power consumption. Furthermore, the reliability problem is also avoided at a standard supply voltage. The idea of currentreuse VCO-buffer is then extended to a compact low power hybrid class-B/C quadrature VCO (QVCO) with enhanced locking time. By using the passive capacitive-coupling between the tail nodes of the class-C cores, quadrature-outputs are achieved without extra power and phase-noise penalties. Moreover, the locking time is significantly reduced by dynamically biasing the auxiliary class-B core during the startup using a four-phase amplitude-detector feedback loop. Fabricated in 65 nm viii CMOS process, the differential VCO-buffer achieves a frequency tuning range from 5.64 to 6.48 GHz (13.89%) and a phase-noise of –108.84 dBc/Hz at 1-MHz offset while dissipating only 3.6 mW at a 1.2 V supply. The QVCO-buffer achieves a phase-noise of – 99.37 dBc/Hz at 1-MHz offset when operating at 9.14 GHz with a power consumption of 10.5 mW at a 1.2 V supply and a small area of 0.137 mm 2 . Secondly, a low voltage back-gate coupled 8-phase current-reuse VCO topology is proposed for 10 GHz beamforming satellite receivers. The current-reuse topology significantly reduces the VCO power consumption. Operating at the low supply voltage of 0.5 V, the VCO outputs and the back-gates of next stage are directly connected without using the lossy DC biasing network, which increases the coupling strength at high frequency. Simulated in 65 nm CMOS process, the proposed 8-phase VCO achieves a frequency tuning range from 8.55 to 11.88 GHz (32.5%) and a phase noise of –114 dBc/Hz at 1-MHz offset while dissipating only 2 mW at a 0.5 V supply, which corresponds to a figure-of-merit (FOM) of 189.5 dBc/Hz. Finally, this work concludes with the design of a current-reuse class-B/C hybrid VCO to achieve robust startup, enhanced phase-noise and differential balancing with small area and power consumption. Fabricated in 65 nm CMOS, the 0.07 mm 2 VCO prototype achieves a frequency tuning range from 10.15 to 11.2 GHz and a phase noise of –107.73 dBc/Hz at 1-MHz offset, while dissipating only 2.2 mW at a 1.2 V supply.
Issue Date
Amin, Md. Tawfiq
Faculty of Science and Technology
Department of Electrical and Computer Engineering
Wireless communication systems
Voltage-controlled oscillators
Electrical and Computer Engineering -- Department of Electrical and Computer Engineering

Martins Rui Paulo
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