UM E-Theses Collection (澳門大學電子學位論文庫)
Applying the novel high speed robust level converter to a 12-bit successive approximation analog-to-digital converters with dual supply domain
English Abstract
The market growth of portable devices is increasing which means that low power circuit design in digital and mixed signal area become more popular nowadays. Power consumption is one of the challenge for portable devices while usually it can be saved significantly if we design them using low supply voltage domain. Moreover, recent research has shown that typical successive approximation register analog-to-digital converter (SAR ADC) can be scaled by lower supply voltage. However, the design complexity increases when resolution is getting higher. In this thesis work, we propose a high speed robust low voltage level converter which is applied to the design of a 12-bit SAR ADC. The ADC architecture is simple and it is designed in two supply domain. A novel level converter is introduced for which it can transform high speed clock signal without degradation of ADC performance. We show that by designing the precise analog parts of SAR ADC using thick oxide devices, design complexity can be relaxed. Simulation results demonstrate the proposed level works perfectly when it is applied to the design of a 12-bit SAR ADC.
Issue Date
Lei, Cheok Teng
Faculty of Science and Technology
Department of Electrical and Computer Engineering
Analog-to-digital converters
Low voltage integrated circuits
Electrical and Computer Engineering -- Department of Electrical and Computer Engineering

U SengPan
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