UM E-Theses Collection (澳門大學電子學位論文庫)

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High-resolution passive and active-passive switched-capacitor delta-sigma modulator design techniques in nanoscale CMOS

English Abstract

High-resolution analog-to-digital converter (ADCs) serves as a critical block in many portable communication and consumer electronic systems. However, the high accuracy analog front-end circuit demands much large power consumption due to the power hungry amplifier. The switched-capacitor (SC) delta-sigma modulator (∆ΣM) ADC can achieve high-resolution. However, it demands high power operational amplifier (Op-Amps) to suppress circuit non-idealities. The advanced nanometer CMOS technology scaling is much compatible for digital circuit while analog circuit suffers design challenges due to a low intrinsic gain of the transistor. This thesis focuses on the Noise transfer function (NTF) zero compensation technique for passive and active-passive ∆ΣM to improve the noise shaping performance. This proposes a positive feedback across passive SC integrator, which shifts the zeroes of NTF of the proposed passive ∆ΣM toward DC on the unit circle in the z-domain and provides maximum attenuation to the quantization noise. Firstly, this technique applies to single loop multi-bit second-order passive ∆ΣMs analyzed mathematically and comprehensive simulation results are provided, to confirm the noise shaping enhancement. In addition, the multi-bit second-order hybrid ∆ΣM is also proposed to take advantage of the front-end Op-Amp, while its numerator coefficient is scaled for very small power consumption. Finally, break the power and resolution tradeoffs for active-passive SC ∆ΣM based on the low gain amplifier and passive SC integrator. An integrator with the low gain open loop amplifier is proposed with built-in positive feedback across passive SC integrator, which requires a DC gain of 14-16 dB. An adder-assisted technique is also proposed to reduce the power of the first amplifier. The proposed design is fabricated in 65nm CMOS technology achieving 91 dB of peak dynamic range, 88.4 dB of peak iii signal to noise (SNR), 88.2 dB of peak signal to noise plus distortion ratio (SNDR), 106 dB of peak signal to spurious-free dynamic range (SFDR) within a 25 kHz signal bandwidth with an active core area of 0.1 mm2 dissipating 73.6µW of power from 1V supply. Due to proposed circuit techniques, the power reduction is significant the Walden Figure-of-Merit (FOMW) is 70fJ/Con-Step) and Schreier Figure-of-Merit (FOMS) is 173.

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Hussain, Arshad


Faculty of Science and Technology


Department of Electrical and Computer Engineering




Analog-to-digital converters

Modulators (Electronics)


U, Seng-Pan

Sin, Sai-Weng

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