Miniaturized wireless electrocardiogram (ECG) sensor systems are keenly demanded for healthcare, offering convenient user experience and the opportunity for wearable long-term monitoring. A key design challenge of the wireless sensor systems is to reduce the power consumption for battery life, while maintaining the system performances. Both academic and industrial sectors are heavily investing on low power technologies. This research focuses on application-specific CMOS ECG signal processing processor designs. Three designs are proposed: 1) By observing the system power budgets, wireless data transmission normally consumes a large portion of the available power. To reduce the data amount, the ECG QRS detection processor is designed and fabricated. It can detect the QRS characteristic point at high accuracy consuming only 0.83 µW power. It provides an option for transmitting only the QRS point information reducing by 6-fold the total system power; 2) To further reduce processor power consumption from the underlying circuit level, sub-/near-threshold digital circuits are designed. They can be employed as a standard cell library for implementing the digital processor with high energy efficiency. The design methodology considered the Low Power-Delay Product, leveraging Inverse Narrow Width effect and robustness; 3) To fulfill the need of the compressed raw ECG signal, a low-voltage ECG data compression processor is designed and fabricated. It compresses the ECG signal in real-time with tunable compression ratio and low distortion, operating at 0.45 V with power consumption as low as 214 nW. The optimization techniques used in the processors design exhibit a vertical hierarchy defined from the algorithm, to the architecture and circuit level. iv In these designs, low complexity algorithms and optimized architectures, as well as the low voltage circuit techniques, are implemented and demonstrated.