ANALOG-TO-DIGITAL CONVERTERS (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary tp be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption of portable devices which are inevitably large if the corresponding signal-conditioning circuits are implemented with discrete or individual off chip analog elements. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. This thesis will propose new techniques tailored for low-voltage and high-speed Switched Capacitor (SC) circuits with various design-specific considerations. Initially, this work will focus on the analysis of the impact of low-voltage deep-submicron CMOS restrictions in analog integrated circuit design (especially under the true low-voltage definition of VDD＜Vthn+丨Vthp丨+2VOV). Subsequently, several generalized and compensative solutions to cope with various types of low-voltage problems will be proposed, namely to overcome Common-Mode Feedback (CMFB), input interface, level-shifting, increased process-sensitivity as a result of reduced supply headroom and overdrive voltage, as well as finite gain-and-offset errors. On the other hand, time interleaving can be considered as one of the most effective methods to increase the overall speed of sampled-data systems, it also presents several tradeoffs in terms of performance degradation, specifically derived from channel mismatches. These mismatch effects will be thoroughly analyzed in the second part of this thesis, where closed-form spectrum and Signal-to-Noise-and-Distortion Ratio (SNDR) formulas for offset, gain, timing and bandwidth mismatches will be derived. These are useful for determining the specifications of various building blocks, during the early design phase, which could be consequently designed with targeting the suppression of channel mismatch non-idealities. Finally, this thesis will address a custom-made implementation of a 1.2-V, 10-b 60-360MS/s reconfigurable time-interleaved pipelined ADC in 0.18μm CMOS, encompassing all the design techniques presented before. The implementation details will be discussed with full behavioral, transistor-level and layout-extracted simulations, and the experimental results of the real chip prototype exhibit an well match with theory and simulation, confirming the effectiveness of the new aforementioned low-voltage high-speed circuit techniques.