INTEGRATION of high-frequency analog filtering into the system Analog Front-End (AFE) is increasingly demanded for the ever growing high-speed communications and signal processing solutions with the corresponding advances in Integrated Circuit (IC) technology. Although the AFEs represent a small portion of the total mixed-signal system chip, they usually are the speed and performance bottleneck of the system. Especially, the design of the AFE's becomes more and more challenging due to the continuous lowering of the supply and increasing of the operation speed, as well as noisying of the working environment driven by the constant growing digital signal processing (DSP) core. This work presents a multirate sampled-data interpolation technique and its Switched-Capacitor (SC) implementation for very high frequency filtering (over hundreds of MHz) while having also dual inherent advantages of reducing the speed of the digital-to-analog converter and the DSP core together with the simplification of the post continuous-time smoothing filter. The first part of this work proposes different novel SC multirate polyphase-based interpolation architectures, which efficiently eliminate the traditional sample-and-hold shaping effects at lower input rate, with the optimization in the circuit sensitivity, speed requirement and component count of the active elements, Physical IC technology imperfections related with IC implementation are also investigated thoroughly; and the advanced circuit techniques including gain, offset and mismatch calibrations are also proposed and analyzed to tackle such limitations. The second part focuses on the tailor-made optimum design and implementation in 0.35um CMOS of two SC interpolating filters: one for the baseband and another for the frequency translated mode operation. The first one implements a 3-stage 8-fold $C interpolating filter with 5.5 MHz, bandwidth and 108 Hz output sampling rate for a NTSC/PAL, CCIR 601 digital video at 3 V supply. Another prototype chip is a 2.5 V, 15-tap, 57 MHz SC FIR bandpass interpolating filter with 4-fold frequency up-translation for 22-24 MHz inputs at 80 MHz to 56-58 MHz outputs at 320MHz using in a Direct-Digital Frequency Synthesis (DDFS) system for wireless communication. Its experimental results match splendidly with theoretical expectations1validate the effectiveness of the presented architectural, circuit- and layout-level and optimization schemes wrestling with different design challenges at such high-frequency operation. This prototype filter chip works up to 400 MHz, with still satisfactory performance, and has so far the highest operating frequency, highest filter order and highest center frequency with highest dynamic range under the lowest supply voltage when compared to the previously reported high-frequency CMOS SC filters.

随着半导体集成电路技术的不断进步，将高频模拟滤波集成在系统的模拟前端接口(Analog Front End-AFE)的需要显得越来越紧迫，尤其在当今迅速发展的高速通信和信号处理应用中。尽管模拟前端接口只是混合信号系统芯片(Mixed-Signal System on Chip)的一个较小的部份，但它却往往是制约整个系统的速度与性能的提高的瓶颈。特别是随着电源电压越降越低而工作频率却越升越高的发展趋势，以及系统芯片中数字信号处理(DSP)比重不断增大所带来数字噪声剧增，模拟前端接口的设计也越来越具挑战性 本论文提出一种用于超高频滤波(>百兆赫兹)的多(抽样)率采样数据(sampled-data)内插技术及其开关电容集成电路的实现。该技术不仅能降低数-模转换器及数字信号处理核的速度，同时还能简化后处理连续时间平滑滤波器。 本论文第一部分首先提出了几种不同的基于多相结构新型多率开关电容内插滤波技术，这些新技术不但能有效地抑制在传统升频滤波系统中所固有的由电路输入端低率采样保持过程所产生的非线性幅频失真，而且对电路所需有源器件的灵敏度、速度及数目需求都进行了优化。另外，本文还对该技术在电路实现过程中所遇到的集成电路技术的物理非理想性做了全面透彻的理论分析与研究，并提出一系列的电路改进技术，如增益、直流失调、元件失配以及自动补偿结构等。 按照以上所提出的理论技术，本论文第二部分集中对工作在基带及频带转移模式两种情况下的开关电容内插滤波器在 0.35微米的 CMOS工艺上经过优化的电路设计及实现分别作了详细的阐述。基带模式的样本电路实现了用于基于CCIR601标准下的NTSC/PAL 数字视讯中的具有5.5MHz带宽、3级(23+8+6抽头)及8倍升频至输出108MHz的低通内插滤波；第二个样本芯片实现了应用在无线通信中直接式数字频率合成(DDFS)系统的一带通内插滤波。该电路工作在 2.5V 电源电压并实现了15 抽头、57MHz中心频率的有限冲激响应(FIR)带通滤波，同时还以4倍升频及频带转移技术实现将采样在 80MHz的 22-24MHz带宽输入信号转移到采样在320MHz的56-58MHz带宽的输出信号。 样本芯片的测试结果与理论值完全一致，这成功地验证了为解决电路在高频工作的设计问题所提出的一系列内插滤波的系统结构、集成电路及版图优化技术的有效性。 该滤波器芯片不仅能以出色的性能有效地工作至400MHz，并且与目前已发表的CMOS 高频开关电容滤波器相比较，具有最高的工作频率、最高的滤波器阶数、最高的中心频率及最高的动态范围同时还具有最低的工作电源电压。