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UM E-Theses Collection (澳門大學電子學位論文庫)

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Title

Low power high efficiency excess-loop-delay compensation techniques in continuous-time delta-sigma modulators

English Abstract

Because of the convenient and powerful function of mobile telecommunication devices, the demand of it is tremendously increased in the whole world wide nowadays. As the connection element between the analog and digital signal world, the modulators are obligatory. On account of the merits of low power consumption, small silicon area, large signal bandwidth, and also inherent anti-aliasing function, the Continuous-Time (CT) ΣΔ modulator has been extensively used in wideband telecommunication systems. However, the performance of CT ΣΔ modulators is restricted by the nonidealities of practical circuit elements. Excess Loop Delay (ELD) is one of the dominant effects induces the error in the Transfer Function, and then reduces the performance of the CT ΣΔ modulator. Even worse, the error may cause the instability of the modulator. This thesis proposes three different techniques with the properties of low-power and high-efficiency to compensate the ELD effect of CT ΣΔ modulators. The first technique is based on the Gm-C loop filter and with one passive resister added. After verifying it in 65nm CMOS technique, the proposed technique can reduce the power consumption up to 32% and compensate up to half of clock cycle delay amount. The second technique employs digital logic elements and an RC feedback network for the active-RC loop filter to track the amount of ELD up to half of clock cycle synchronously on a real-time modulator, and then compensate it. It is verified in 65nm CMOS process, compare with the traditional technique, power reduced from 6.5mW to 5.45mw. And the third technique is for hybrid active-passive integrators. The efficiency of the proposed compensation techniques are implemented in the designed modulators and verified by the transistor-level simulation as well. This technique can compensate the delay amount up to one clock cycle and reduced more than half of power dissipation. Compare with the traditional techniques, these three techniques are quite low power dissipation and can compensate the ELD effect effectively.

Issue date

2013

Author

Cai, Chen Yan

Faculty

Faculty of Science and Technology

Degree

M.Sc.

Subject

Analog-to-digital converters

Modulators (Electronics)

Continuous-time filters

Supervisor

Sin, SaiWeng

U, SengPan

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Location
1/F Zone C
Library URL
991007406589706306